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Dynamically Adapting Floating-Point Precision to Accelerate Deep Neural Network Training.

J. Ríos, A. Armejach, E. Petit, G. Henry, and M. Casas. ICMLA, page 980-987. IEEE, (2021)

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Techniques to improve performance in requester-wins hardware transactional memory.A. Armejach, J. Gil, A. Negi, O. Unsal, and A. Cristal. TACO, 10 (4): 42:1-42:25 (2013)Dynamically Adapting Floating-Point Precision to Accelerate Deep Neural Network Training.J. Ríos, A. Armejach, E. Petit, G. Henry, and M. Casas. ICMLA, page 980-987. IEEE, (2021)Circuit design of a dual-versioning L1 data cache.A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur, and M. Valero. Integration, 45 (3): 237-245 (2012)Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory.O. Arcas-Abella, A. Armejach, T. Hayes, G. Malazgirt, O. Palomar, B. Salami, and N. Sönmez. Computing in Science and Engineering, 18 (1): 80-87 (2016)Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.A. Armejach, A. Seyedi, J. Gil, I. Hur, A. Cristal, O. Unsal, and M. Valero. PACT, page 361-371. IEEE Computer Society, (2011)EazyHTM: eager-lazy hardware transactional memory.S. Tomic, C. Perfumo, C. Kulkarni, A. Armejach, A. Cristal, O. Unsal, T. Harris, and M. Valero. MICRO, page 145-155. ACM, (2009)Design Space Exploration of Next-Generation HPC Machines.C. Gómez, F. Martínez, A. Armejach, M. Moretó, F. Mantovani, and M. Casas. IPDPS, page 54-65. IEEE, (2019)Transactional prefetching: narrowing the window of contention in hardware transactional memory.A. Negi, A. Armejach, A. Cristal, O. Unsal, and P. Stenström. PACT, page 181-190. ACM, (2012)Circuit design of a dual-versioning L1 data cache for optimistic concurrency.A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur, and M. Valero. ACM Great Lakes Symposium on VLSI, page 325-330. ACM, (2011)HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory.A. Armejach, A. Negi, A. Cristal, O. Unsal, P. Stenström, and T. Harris. HiPC, page 196-205. IEEE Computer Society, (2013)

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Disambiguation of "Armejach, Adrià"

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Dynamically Adapting Floating-Point Precision to Accelerate Deep Neural Network Training.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Dynamically Adapting Floating-Point Precision to Accelerate Deep Neural Network Training.

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Dynamically Adapting Floating-Point Precision to Accelerate Deep Neural Network Training.