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Approaching Ideal NoC Latency with Pre-Configured Routes., , and . NOCS, page 153-162. IEEE Computer Society, (2007)Variable-width datapath for on-chip network static power reduction., and . NOCS, page 96-103. IEEE, (2014)Extending Summation Precision for Network Reduction Operations., , , and . International Journal of Parallel Programming, 43 (6): 1218-1243 (2015)Adaptive Backpressure: Efficient buffer management for on-chip networks., , , and . ICCD, page 419-426. IEEE Computer Society, (2012)The Pitfalls of Provisioning Exascale Networks: A Trace Replay Analysis for Understanding Communication Performance., , , , and . ISC, volume 10876 of Lecture Notes in Computer Science, page 269-288. Springer, (2018)Extending classical processors to support future large scale quantum accelerators., , , and . CF, page 317. ACM, (2019)Evaluating Elastic Buffer and Wormhole Flow Control., , and . IEEE Trans. Computers, 60 (6): 896-903 (2011)OpenSoC Fabric: On-Chip Network Generator: Using Chisel to Generate a Parameterizable On-Chip Interconnect Fabric., , , and . NoCArc@MICRO, page 45-50. ACM, (2014)Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks., , , and . IEEE Comput. Archit. Lett., 10 (2): 33-36 (2011)Bandwidth steering in HPC using silicon nanophotonics., , , , , , , , , and 1 other author(s). SC, page 41:1-41:25. ACM, (2019)