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Disambiguation of "Bernardi, Paolo"

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An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs.

, , , , and . DDECS, page 258-263. IEEE Computer Society, (2009)

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PD Dr. Paolo Malgaretti University of Stuttgart

Paolo Carlo Danesini University of Stuttgart

 

Other publications of authors with the same name

Test Considerations about the Structured ASIC Paradigm., and . DDECS, page 232-233. IEEE Computer Society, (2006)An I-IP based approach for the monitoring of NBTI effects in SoCs., , , , , , and . IOLTS, page 15-20. IEEE Computer Society, (2009)An Adaptive Low-Cost Tester Architecture Supporting Embedded Memory Volume Diagnosis., and . IEEE Trans. Instrumentation and Measurement, 61 (4): 1002-1018 (2012)An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (3): 570-574 (2008)Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test., , , , and . J. Electronic Testing, 30 (3): 317-328 (2014)A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques., , , , , , and . J. Electronic Testing, 20 (1): 79-87 (2004)An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors., , , , and . DFT, page 445-453. IEEE Computer Society, (2005)SW-based transparent in-field memory testing., , , and . LATS, page 1-6. IEEE Computer Society, (2015)An effective approach to automatic functional processor test generation for small-delay faults., , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Scan-chain intra-cell defects grading., , , , , , and . DTIS, page 1-6. IEEE, (2015)