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Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation".

, , , , , and . J. Solid-State Circuits, 46 (3): 705 (2011)

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Power-efficient medical image processing using PUMA., , and . SASP, page 29-34. IEEE Computer Society, (2009)A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation., , , and . CICC, page 1-4. IEEE, (2013)Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache., , , , , , and . CGO, page 179-190. IEEE Computer Society, (2005)PEPSC: A Power-Efficient Processor for Scientific Computing., , , and . PACT, page 101-110. IEEE Computer Society, (2011)A Deep Dive Into Understanding The Random Walk-Based Temporal Graph Learning., , , , , , , , and . IISWC, page 87-100. IEEE, (2021)Bridging the computation gap between programmable processors and hardwired accelerators., , , and . HPCA, page 313-322. IEEE Computer Society, (2009)A Customized Processor for Energy Efficient Scientific Computing., , , and . IEEE Trans. Computers, 61 (12): 1711-1723 (2012)CoreGenesis: erasing core boundaries for robust and configurable performance., , , , and . PACT, page 571-572. ACM, (2010)DVFS in loop accelerators using BLADES., , , , and . DAC, page 894-897. ACM, (2008)Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation"., , , , , and . J. Solid-State Circuits, 46 (3): 705 (2011)