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FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths.

, , , , , and . CGO, page 201-212. IEEE Computer Society, (2004)

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Systematic Register Bypass Customization for Application-Specific Processors., , , , , , and . ASAP, page 64-74. IEEE Computer Society, (2003)Investigating Data Layout Transformations in Chapel., , and . IPDPS Workshops, page 915-924. IEEE Computer Society, (2018)Taming irregular applications via advanced dynamic parallelism on GPUs., , , , and . CF, page 146-154. ACM, (2018)Code and data partitioning for fine-grain parallelism., and . LCTES, page 161-164. ACM, (2007)An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors., , , , , and . ISCA, page 272-283. IEEE Computer Society, (2005)Adaptive Task Aggregation for High-Performance Sparse Solvers on GPUs., , , , and . PACT, page 324-336. IEEE, (2019)Cost-Sensitive Partitioning in an Architecture Synthesis System for Multicluster Processors., , , and . IEEE Micro, 24 (3): 10-20 (2004)Compiler-directed Data Partitioning for Multicluster Processors., and . CGO, page 208-220. IEEE Computer Society, (2006)Extended task queuing: active messages for heterogeneous systems., , , , , , , , , and 6 other author(s). SC, page 933-944. IEEE Computer Society, (2016)Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures., , and . MICRO, page 369-380. IEEE Computer Society, (2007)