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A content-aware writing mechanism for reducing energy on non-volatile memory based embedded storage systems.

, , , , and . Design Autom. for Emb. Sys., 17 (3-4): 711-737 (2013)

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Optimal scheduling to minimize non-volatile memory access time with hardware cache., , , , and . VLSI-SoC, page 131-136. IEEE, (2010)Probabilistic Rotation: Scheduling Graphs with Uncertain Execution Time., , , and . ICPP, page 292-297. IEEE Computer Society, (1997)Timing Optimization of Nested Loops Considering Code Size for DSP Applications., , and . ICPP, page 475-482. IEEE Computer Society, (2004)Optimal Data Allocation for Scratch-Pad Memory on Embedded Multi-core Systems., , , , and . ICPP, page 464-471. IEEE Computer Society, (2011)Polynomial-Time Nested Loop Fusion with Full Parallelism., , and . ICPP, Vol. 3, page 9-16. IEEE Computer Society, (1996)0-8186-7623-X.Full Parallelism in Uniform Nested Loops Using Multi-Dimensional Retiming., and . ICPP (2), page 130-133. CRC Press, (1994)Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP., , , , , and . J. Parallel Distrib. Comput., 68 (4): 443-455 (2008)Communication Scheduling With Re-Routing Based On Static And Hybrid Techniques., , and . Journal of Circuits, Systems, and Computers, 13 (5): 1039-1064 (2004)A novel multiplexer-based low-power full adder., , , , and . IEEE Trans. on Circuits and Systems, 51-II (7): 345-348 (2004)Optimized Address Assignment With Array and Loop Transformations for Minimizing Schedule Length., , , , and . IEEE Trans. on Circuits and Systems, 55-I (1): 379-389 (2008)