%0 Journal Article %1 journals/tcas/XueJSWS08 %A Xue, Chun Jason %A Jia, Zhiping %A Shao, Zili %A Wang, Meng %A Sha, Edwin Hsing-Mean %D 2008 %J IEEE Trans. on Circuits and Systems %K dblp %N 1 %P 379-389 %T Optimized Address Assignment With Array and Loop Transformations for Minimizing Schedule Length. %U http://dblp.uni-trier.de/db/journals/tcas/tcasI55.html#XueJSWS08 %V 55-I

@article{journals/tcas/XueJSWS08, added-at = {2011-11-04T00:00:00.000+0100}, author = {Xue, Chun Jason and Jia, Zhiping and Shao, Zili and Wang, Meng and Sha, Edwin Hsing-Mean}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2c803f7e2096e930e35fc9367cb490c21/dblp}, ee = {http://dx.doi.org/10.1109/TCSI.2007.913721}, interhash = {da0e67f3a379e6fead5553da26f1de7d}, intrahash = {c803f7e2096e930e35fc9367cb490c21}, journal = {IEEE Trans. on Circuits and Systems}, keywords = {dblp}, number = 1, pages = {379-389}, timestamp = {2016-02-02T02:19:49.000+0100}, title = {Optimized Address Assignment With Array and Loop Transformations for Minimizing Schedule Length.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasI55.html#XueJSWS08}, volume = {55-I}, year = 2008 }