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Models of Communication for Multicore Processors., , and . ISORC Workshops, page 9-16. IEEE Computer Society, (2015)Fast, Interactive Worst-Case Execution Time Analysis With Back-Annotation., , , , , and . IEEE Trans. Industrial Informatics, 8 (2): 366-377 (2012)Direct garbage collection: two-fold speedup for managed language embedded systems., and . IJES, 10 (5): 394-405 (2018)Time-Predictable Computer Architecture.. EURASIP J. Emb. Sys., (2009)Worst-Case Analysis of Heap Allocations., , and . ISoLA (2), volume 6416 of Lecture Notes in Computer Science, page 464-478. Springer, (2010)A time-predictable branch predictor., , and . SAC, page 607-616. ACM, (2019)Hardlock: A Concurrent Real-Time Multicore Locking Unit., and . ISORC, page 9-16. IEEE Computer Society, (2018)A Time Predictable Instruction Cache for a Java Processor.. OTM Workshops, volume 3292 of Lecture Notes in Computer Science, page 371-382. Springer, (2004)A Single-Path Chip-Multiprocessor System., , and . SEUS, volume 5860 of Lecture Notes in Computer Science, page 47-57. Springer, (2009)Scala for Real-Time Systems?. JTRES, page 13:1-13:5. ACM, (2015)