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Disambiguation of "Paim, Guilherme"

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Compact CMOS-Compatible Majority Gate Using Body Biasing in FDSOI Technology

, , , , , , and . IEEE journal on emerging and selected topics in circuits and systems, 13 (1): 86-95 (2023)
DOI: 10.1109/JETCAS.2023.3243150

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Other publications of authors with the same name

A multi-standard interpolation filter for motion compensated prediction on high definition videos., , , , , and . LASCAS, page 1-4. IEEE, (2015)High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator., , , , , and . J. Real-Time Image Processing, 16 (1): 175-192 (2019)A power-predictive environment for fast and power-aware ASIC-based FIR filter design., , , , , and . SBCCI, page 168-173. ACM, (2017)Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors., , , , , , and . NEWCAS, page 309-312. IEEE, (2018)High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards., , , , , and . ICIP, page 2162-2166. IEEE, (2016)Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers., , , , and . ICECS, page 478-481. IEEE, (2017)Boosting the Efficiency of the Harmonics Elimination VLSI Architecture by Arithmetic Approximations., , , , and . ICECS, page 1-4. IEEE, (2021)Bridging the Gap Between Voltage Over-Scaling and Joint Hardware Accelerator-Algorithm Closed-Loop, , , , and . IEEE transactions on circuits and systems for video technology, 32 (1): 398-410 (2022)Power efficient 2-D rounded cosine transform with adder compressors for image compression., , , and . ICECS, page 348-351. IEEE, (2015)A Fixed-Point Natural Logarithm Approximation Hardware Design Using Taylor Series., , , and . NGCAS, page 53-56. IEEE, (2018)