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The optimization of parallel Smith-Waterman sequence alignment using on-chip memory of GPGPU.

Q. Zhang, H. An, G. Liu, W. Han, P. Yao, M. Xu, and X. Li. BIC-TA, page 844-850. IEEE, (2010)

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Hong Chen University of Stuttgart

Jun. -Prof. Sungkun Hong University of Stuttgart

Mahathi Anand University of Stuttgart

Fatemeh Ansari University of Stuttgart

Jun. -Prof. Sun Hea Hong University of Stuttgart

Other publications of authors with the same name

The Mapping Framework and Optimizing Strategy for Block Cryptography Algorithms on Cell Broadband Engine.M. Xu, H. An, G. Liu, Y. Wang, G. Xu, P. Yao, X. Hao, and W. Han. PDCAT, page 42-47. IEEE Computer Society, (2009)Efficient execution of speculative threads and transactions with hardware transactional memory.G. Li, H. An, Q. Li, B. Deng, and W. Dai. Future Generation Comp. Syst., (2014)The optimization of parallel Smith-Waterman sequence alignment using on-chip memory of GPGPU.Q. Zhang, H. An, G. Liu, W. Han, P. Yao, M. Xu, and X. Li. BIC-TA, page 844-850. IEEE, (2010)A Priority-Aware NoC to Reduce Squashes in Thread Level Speculation for Chip Multiprocessors.W. Dai, H. An, Q. Li, G. Li, B. Deng, S. Wu, X. Li, and Y. Liu. ISPA, page 87-92. IEEE Computer Society, (2011)A Non-blocking Programming Framework for Pipeline Application on Multi-core Platform.X. Li, H. An, G. Liu, W. Han, M. Xu, W. Zhou, and Q. Li. ISPA, page 25-30. IEEE Computer Society, (2011)Priority-based squash reducing methods in thread level speculation.Q. Li, H. An, W. Dai, G. Li, B. Deng, Y. Liu, X. Li, and S. Wu. IJITCC, 2 (2): 138-154 (2012)Scaling the Performance of Tiled Processor Architectures with On-Chip-Network Topology.Y. Ren, H. An, M. Cong, G. Xu, and L. Wang. CSO (1), page 77-81. IEEE Computer Society, (2009)Investigation of Factors Impacting Thread-Level Parallelism from Desktop, Multimedia and HPC Applications.Y. Wang, H. An, J. Yan, Q. Li, W. Han, L. Wang, and G. Liu. FCST, page 27-32. IEEE Computer Society, (2009)Parallelizing Back Propagation Neural Network on Speculative Multicores.Y. Wang, H. An, Z. Liu, T. Liu, and D. Zhao. ICPADS, page 902-907. IEEE, (2016)Refactoring the Molecular Docking Simulation for Heterogeneous, Manycore Processors Systems.J. Chen, H. Lin, W. Liang, Y. Yu, W. Han, H. An, Y. Chen, and X. Liu. ISPA/IUCC, page 1031-1038. IEEE, (2017)

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Disambiguation of "An, Hong"

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The optimization of parallel Smith-Waterman sequence alignment using on-chip memory of GPGPU.

Please choose a person to relate this publication to

Hong Chen University of Stuttgart

Jun. -Prof. Sungkun Hong University of Stuttgart

Mahathi Anand University of Stuttgart

Fatemeh Ansari University of Stuttgart

Jun. -Prof. Sun Hea Hong University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "An, Hong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML The optimization of parallel Smith-Waterman sequence alignment using on-chip memory of GPGPU.

Please choose a person to relate this publication to

Hong Chen University of Stuttgart

Jun. -Prof. Sungkun Hong University of Stuttgart

Mahathi Anand University of Stuttgart

Fatemeh Ansari University of Stuttgart

Jun. -Prof. Sun Hea Hong University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

The optimization of parallel Smith-Waterman sequence alignment using on-chip memory of GPGPU.