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Efficient execution of speculative threads and transactions with hardware transactional memory.

, , , , and . Future Generation Comp. Syst., (2014)

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Value Predicted LogSPoTM: Improve the Parallesim of Thread Level System by Using a Value Predictor., , , , and . ACIS-ICIS, page 130-135. IEEE Computer Society, (2012)Distributed Control Independence for Composable Multi-processors., , , , , , and . ACIS-ICIS, page 124-129. IEEE Computer Society, (2012)Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems., , , , , and . IEEE Trans. Computers, 71 (3): 613-627 (2022)Computationally-redundant energy-efficient processing for y'all (CREEPY)., , , , , , and . ICRC, page 1-8. IEEE Computer Society, (2016)Energy efficiency limits of logic and memory., , , , , , , , , and . ICRC, page 1-8. IEEE Computer Society, (2016)Distributed replay protocol for distributed uniprocessors., , , , , , and . ICS, page 3-14. ACM, (2012)SeTM: Efficient Execution of Speculative Threads with Hardware Transactional Memory., , , , and . ICPADS, page 522-531. IEEE Computer Society, (2012)A Brief Survey of Non-Residue Based Computational Error Correction., , and . CoRR, (2016)A Priority-Aware NoC to Reduce Squashes in Thread Level Speculation for Chip Multiprocessors., , , , , , , and . ISPA, page 87-92. IEEE Computer Society, (2011)Extending Moore's Law via Computationally Error-Tolerant Computing., , , , , , and . TACO, 15 (1): 8:1-8:27 (2018)