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Disambiguation of "Bowman, Keith A."

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Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance.

, , , , , , , and . ISSCC, page 402-403. IEEE, (2008)

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A. Laukemann

Allison Keith University of Stuttgart

A. Laukemann

A. Laukemann

A. Vo{\ss}

 

Other publications of authors with the same name

Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)Welcome to ISQED 2013., , , , , , , and . ISQED, IEEE, (2013)Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)., , , and . IEEE Trans. VLSI Syst., 9 (6): 899-912 (2001)A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors., , , , , , , , , and 4 other author(s). ISSCC, page 316-318. IEEE, (2019)Circuit techniques for dynamic variation tolerance., , , , , , and . DAC, page 4-7. ACM, (2009)A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains., , , , , , , and . J. Solid-State Circuits, 54 (4): 1173-1184 (2019)An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor., , , , , , , and . VLSI Circuits, page 65-66. IEEE, (2018)A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance., , , , , , , , , and 1 other author(s). ISSCC, page 282-283. IEEE, (2010)Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 46 (1): 184-193 (2011)Resilient design in scaled CMOS for energy efficiency., , , , , , , , , and 2 other author(s). ASP-DAC, page 625. IEEE, (2010)