Author of the publication

Degradability Enabled Routing for Network-on-Chip Switches

, , and . it - Information Technology, 52 (4): 201--208 (2010)
DOI: 10.1524/itit.2010.0592

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Cost-Based Deflection Routing for Intelligent NoC Switches, and . Lecture Notes in Electrical Engineering, (2011)Fault-Tolerant Architecture and Deflection Routing for Degradable NoC Switches, and . Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip, (2009)Modellierung und Simulation von Networks-on-Chip mit OSCI TLM2, and . Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, (2009)Optimized Reduce for Mesh-Based NoC Multiprocessors, and . Proceedings of the International Parallel & Distributed Processing Symposium, Workshops & PhD forum (IPDPSW '12), (2012)Low-Latency Collectives for the Intel SCC, , , and . Proceedings of the International Conference on Cluster Computing (CLUSTER '12), (2012)Fault Tolerant Network on Chip Switching with Graceful Performance Degradation, , and . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29 (6): 883--896 (2010)A SystemC TLM2 Model of Communication in Wormhole Switched Networks-on-Chip, and . Proceedings of the Forum on Specification and Design Languages, (2009)Degradability Enabled Routing for Network-on-Chip Switches, , and . it - Information Technology, 52 (4): 201--208 (2010)Minimal MPI as Programming Interface for Multicore System-on-Chips, , , and . Proceedings of the Forum on Specification and Design Languages (FDL '12), (2012)