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Reliability Modeling and Management of Nanophotonic On-Chip Networks., , , , , , , , , and 1 other author(s). IEEE Trans. VLSI Syst., 20 (1): 98-111 (2012)Global On-Chip Coordination at Light Speed., , , , , , , , and . IEEE Design & Test of Computers, 27 (4): 54-67 (2010)A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis., , , , , , and . FPL, page 556-561. IEEE Computer Society, (2010)A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture., , , , and . ASAP, page 371-376. IEEE Computer Society, (2007)A Video Specific Instruction Set Architecture for ASIP design., , , and . VLSI Design, (2007)MOPED: Accelerating Data Communication on Future CMPs., , , and . IEEE Micro, 31 (4): 42-50 (2011)On-Chip Systolic Networks for Real-Time Tracking of Pairwise Correlations Between Neurons in a Large-Scale Network., , , , and . IEEE Trans. Biomed. Engineering, 60 (1): 198-202 (2013)Heuristic on a Novel Power Management System Cooperating with Compiler., , , , and . J. Low Power Electron., 3 (1): 22-27 (2007)A Retargetable Compiler of VLIW ASIP for Media Signal Processing., , , and . ESA, page 46-52. CSREA Press, (2006)An Optimizing Search Method of Systolic Array Design., and . IASTED PDCS, page 573-577. IASTED/ACTA Press, (2002)