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Incremental Verification with Error Detection, Diagnosis, and Visualization., , , and . IEEE Design & Test of Computers, 26 (2): 34-43 (2009)Physical Synthesis with Clock-Network Optimization for Large Systems on Chips., , , , , , and . IEEE Micro, 31 (4): 51-62 (2011)InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization., , , and . ISQED, page 487-494. IEEE Computer Society, (2007)Speeding Up Physical Synthesis with Transactional Timing Analysis., , , and . IEEE Design & Test of Computers, 27 (5): 14-25 (2010)Capo: robust and scalable open-source min-cut floorplacer., , , , , , and . ISPD, page 224-226. ACM, (2005)Satisfying whitespace requirements in top-down placement., , , and . ISPD, page 206-208. ACM, (2006)Hypergraph Partitioning and Clustering., and . Handbook of Approximation Algorithms and Metaheuristics, Chapman and Hall/CRC, (2007)Utility of the OpenAccess database in academic research., , and . ASP-DAC, page 440-441. IEEE, (2006)Min-cut floorplacement., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (7): 1313-1326 (2006)Ultra-fast interconnect driven cell cloning for minimizing critical path delay., , , , , , and . ISPD, page 75-82. ACM, (2010)