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Disambiguation of "Chang, Yao-Wen"

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Temporal floorplanning using the three-dimensional transitive closure subGraph.

, , and . ACM Trans. Design Autom. Electr. Syst., 12 (4): 37 (2007)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yao Wang University of Stuttgart

Ingeborg Wenger University of Stuttgart

Dr. rer. nat. Tim Wendlandt University of Stuttgart

Dr. -Ing. Christoph Wenzel University of Stuttgart

Florian Wendt University of Stuttgart

 

Other publications of authors with the same name

Placement with Alignment and Performance Constraints Using the B*-Tree Representation., and . ICCD, page 568-571. IEEE Computer Society, (2004)RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction., , and . ISCAS (4), page 4134-4137. IEEE, (2005)Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability., , , , , and . ASP-DAC, page 238-243. IEEE Computer Society, (2007)TCG-S: orthogonal coupling of P/sup */-admissible representations for general floorplans., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (6): 968-980 (2004)Matching-based algorithm for FPGA channel segmentation design., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 20 (6): 784-791 (2001)MR: a new framework for multilevel full-chip routing., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (5): 793-800 (2004)Timing-driven routing for symmetrical-array-based FPGAs., , and . ICCD, page 628-633. (1998)Global Interconnect Planning., , and . Handbook of Algorithms for Physical Design Automation, Auerbach Publications, (2008)ECO Timing Optimization Using Spare Cells and Technology Remapping., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (5): 697-710 (2010)Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (2): 224-236 (2014)