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Disambiguation of "Roy, Sujoy Sinha"

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HEPCloud: An FPGA-Based Multicore Processor for FV Somewhat Homomorphic Function Evaluation.

, , , , and . IEEE Trans. Computers, 67 (11): 1637-1650 (2018)

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Sakshi Sinha University of Stuttgart

Ph. D. Sarbani Roy University of Stuttgart

Rajarshi Roy University of Stuttgart

Ranjith Mathew Roy University of Stuttgart

 

Other publications of authors with the same name

High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems., , , , , , and . IEEE Trans. on Circuits and Systems, 62-I (1): 157-166 (2015)Pushing the speed limit of constant-time discrete Gaussian sampling. A case study on Falcon., , , and . IACR Cryptology ePrint Archive, (2019)Compact and Side Channel Secure Discrete Gaussian Sampling., , , and . IACR Cryptology ePrint Archive, (2014)Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs., , and . CHES, volume 7428 of Lecture Notes in Computer Science, page 494-511. Springer, (2012)A Parallel Architecture for Koblitz Curve Scalar Multiplications on FPGA Platforms., , and . DSD, page 553-559. IEEE Computer Society, (2012)FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data., , , , and . HPCA, page 387-398. IEEE, (2019)Constant-Time Discrete Gaussian Sampling., , , , and . IEEE Trans. Computers, 67 (11): 1561-1571 (2018)Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed., , and . IEEE Trans. VLSI Syst., 21 (5): 901-909 (2013)Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms., , and . IEEE Trans. VLSI Syst., 23 (5): 810-818 (2015)Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms., , and . IACR Cryptology ePrint Archive, (2013)