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Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors., , , , and . IEEE Trans. VLSI Syst., 22 (4): 747-758 (2014)High-Speed Multioperand Decimal Adders., and . IEEE Trans. Computers, 54 (8): 953-963 (2005)Hardware Designs for Binary Integer Decimal-Based Rounding., , , and . IEEE Trans. Computers, 60 (5): 614-627 (2011)Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support., , and . IEEE Trans. Computers, 58 (2): 175-187 (2009)Binary Integer Decimal-Based Floating-Point Multiplication., , and . IEEE Trans. Computers, 62 (7): 1460-1466 (2013)Achieving Exascale Capabilities through Heterogeneous Computing., , , , , , , , , and . IEEE Micro, 35 (4): 26-36 (2015)A survey of hardware designs for decimal arithmetic., , , , and . IBM Journal of Research and Development, 54 (2): 8 (2010)Hardware interval multipliers.. RITA, 3 (2): 73-90 (1996)Optimal initial approximations for the Newton-Raphson division algorithm., , and . Computing, 53 (3-4): 233-242 (1994)Energy-efficient floating-point arithmetic for digital signal processors., , and . ACSCC, page 1823-1827. IEEE, (2011)