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Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture., , and . The Journal of Supercomputing, 30 (3): 263-282 (2004)Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core., , , , and . FPL, page 562-566. IEEE, (2007)A flexible approach for compiling scilab to reconfigurable multi-core embedded systems., , , , , , , , , and 11 other author(s). ReCoSoC, page 1-8. IEEE, (2012)Reconfigurable Architectures for Adaptable Mobile Systems., and . ERSA, page 17-25. CSREA Press, (2005)A configurable SIMD architecture with explicit datapath for intelligent learning., , , , , , , and . SAMOS, page 156-163. IEEE, (2016)The DeSyRe Project: On-Demand System Reliability., , , , , , , , , and 2 other author(s). DSD, page 335-342. IEEE Computer Society, (2012)Multicore soc for on-board payload signal processing., , , , , and . AHS, page 17-21. IEEE, (2011)Mapping Wireless Communication Algorithms to a Reconfigurable Architecture., , , and . Engineering of Reconfigurable Systems and Algorithms, page 242-251. CSREA Press, (2003)Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture., , , and . ERSA, page 110-116. CSREA Press, (2006)Implementing an Adaptive Viterbi Algorithm in Coarse-Grained Reconfigurable Hardware., , and . ERSA, page 62-70. CSREA Press, (2005)