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Versatile emulation of spiking neural networks on an accelerated neuromorphic substrate., , , , , , , , , and 15 other author(s). CoRR, (2019)The Operating System of the Neuromorphic BrainScaleS-1 System., , , , , , , , , and 12 other author(s). CoRR, (2020)Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model., , , and . IJCNN, page 1-6. IEEE, (2006)Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System., , , , , , , , , and 15 other author(s). CoRR, (2017)Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system., , , , , , , , , and 2 other author(s). ISCAS, page 702. IEEE, (2012)A VLSI Implementation of the Adaptive Exponential Integrate-and-Fire Neuron Model., , , , and . NIPS, page 1642-1650. Curran Associates, Inc., (2010)Demonstrating Hybrid Learning in a Flexible Neuromorphic Hardware System., , , , , and . IEEE Trans. Biomed. Circuits and Systems, 11 (1): 128-142 (2017)An Accelerated LIF Neuronal Network Array for a Large-Scale Mixed-Signal Neuromorphic Architecture., , , , , , , and . IEEE Trans. on Circuits and Systems, 65-I (12): 4299-4312 (2018)Robustness from structure: Inference with hierarchical spiking networks on analog neuromorphic hardware., , , , , and . IJCNN, page 2209-2216. IEEE, (2017)A wafer-scale neuromorphic hardware system for large-scale neural modeling., , , , , and . ISCAS, page 1947-1950. IEEE, (2010)