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Automatic module allocation in high level synthesis.

, , , and . EURO-DAC, page 328-333. IEEE Computer Society Press, (1992)

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Automatic module allocation in high level synthesis., , , and . EURO-DAC, page 328-333. IEEE Computer Society Press, (1992)Automatic generation of interprocess communication in the PARAGON system., , and . RSP, page 24-29. IEEE Computer Society, (1996)Timing preserving interface transformations for the synthesis of behavioral VHDL., and . EURO-DAC, page 618-623. IEEE Computer Society, (1994)CASCH - ein Scheduling-Algorithmus für "High-Level"-Synthese., , and . Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, volume 255 of Informatik-Fachberichte, page 143-156. Springer, (1990)Fast Bit-Accurate C++ Datatypes For Functional System Verification and Synthesis., , and . FDL, page 337-345. ECSI, (2004)Interface specification and synthesis for VHDL processes., and . EURO-DAC, page 152-157. IEEE Computer Society, (1993)CASCH: a scheduling algorithm for "high level"-synthesis., , and . EURO-DAC, page 311-315. EEE Computer Society, (1991)Spezifikation und Synthese aus taktfreien VHDL Verhaltensbeschreibungen.. Eberhard Karls University of Tübingen, (1997)Specification of interface components for synchronous data paths., and . HLSS, page 134-139. ACM, (1994)