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Disambiguation of "Pirsch, Peter"

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Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM.

, , and . Great Lakes Symposium on VLSI, page 42-45. IEEE Computer Society, (1999)

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Elke Peter University of Stuttgart

Univ. -Prof. Dr. Rene Peters University of Stuttgart

Bernd Peters University of Stuttgart

Alexander Peter University of Stuttgart

Schmid. Peter

 

Other publications of authors with the same name

Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms., , and . ASAP, page 294-303. IEEE Computer Society, (1997)A hierarchical multiprocessor architecture based on heterogeneous processors for video coding applications., , and . ICASSP (2), page 413-416. IEEE Computer Society, (1994)A multi-core SoC design for advanced image and video compression., , , , , , and . ICASSP (5), page 665-668. IEEE, (2005)Design Space Exploration of Media Processors: A Parameterized Scheduler., , , and . ICSAMOS, page 41-49. IEEE, (2007)Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures., , , , and . ICSAMOS, page 125-132. IEEE, (2009)The Video and Image Processing Emulation System VIPES., , and . International Workshop on Rapid System Prototyping, page 170-175. IEEE Computer Society, (1998)A Fault-tolerant DCT-Architecture Based on Distributed Arithmetic., , and . ISCAS, page 1583-1586. IEEE, (1993)The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques., , , , , and . VLSI Signal Processing, 11 (1-2): 51-74 (1995)A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications., , and . VLSI Signal Processing, 41 (2): 139-151 (2005)Scalable Multi-Standard LSI Texture Encoder for MPEG and VC-1 Video Compression., , , and . ICME, page 1187-1190. IEEE Computer Society, (2007)