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Systematic stability-analysis method for analog circuits.

, , , and . DATE, page 150-155. European Design and Automation Association, Leuven, Belgium, (2006)

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Design Issues and Considerations for Low-Cost 3-D TSV IC Technology., , , , , , , , , and 27 other author(s). J. Solid-State Circuits, 46 (1): 293-307 (2011)Systematic stability-analysis method for analog circuits., , , and . DATE, page 150-155. European Design and Automation Association, Leuven, Belgium, (2006)Experimental Analysis of the Coupling Mechanisms Between a 4 GHz PPA and a 5-7 GHz LC -VCO., , , , , and . IEEE Trans. Instrumentation and Measurement, 58 (8): 2706-2713 (2009)Design issues and considerations for low-cost 3D TSV IC technology., , , , , , , , , and 24 other author(s). ISSCC, page 148-149. IEEE, (2010)Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors., , , and . IEEE Trans. Instrumentation and Measurement, 59 (6): 1727-1733 (2010)A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (11): 1613-1626 (2009)Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's., , , , and . DATE, page 1520-1525. EDA Consortium, San Jose, CA, USA, (2007)A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS., , , , and . J. Solid-State Circuits, 43 (12): 2651-2659 (2008)A Single-Inductor Dual-Band VCO in a 0.06mm2 5.6GHz Multi-Band Front-End in 90nm Digital CMOS., , , , and . ISSCC, page 324-325. IEEE, (2008)