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Reliability of 8Mbit Embedded-STT-MRAM in 28nm FDSOI Technology.

Y. Ji, H. Goo, J. Lim, S. Lee, S. Lee, T. Uemura, J. Park, S. Han, S. Shin, J. Lee, Y. Song, K. Lee, H. Shin, S. Hwang, B. Seo, Y. Lee, J. Kim, G. Koh, K. Park, S. Pae, G. Jeong, J. Yoon, and E. Jung. IRPS, page 1-3. IEEE, (2019)

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Optimal design of dummy ball array in wafer level package to improve board level thermal cycle reliability (BLR).S. Jeong, J. Kim, A. Kim, B. Kim, M. Lee, J. Chang, I. Baick, H. Kang, Y. Ji, S. Shin and 1 other author(s). IRPS, page 3. IEEE, (2018)SRAM stability design comprehending 14nm FinFET reliability.C. Bae, S. Pae, C. sik Yu, K. Kim, Y. Kim, and J. Park. IRPS, page 13. IEEE, (2015)Systematical study of 14nm FinFET reliability: From device level stress to product HTOL.C. Liu, H. Sagong, H. Kim, S. Choo, H. Lee, Y. Kim, H. Kim, B. Jo, M. Jin, J. Kim and 3 other author(s). IRPS, page 2. IEEE, (2015)Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit.H. Jiang, H. Sagong, J. Kim, J. Park, S. Shin, and S. Pae. IRPS, page 1-5. IEEE, (2019)Reliability characterization of advanced CMOS image sensor (CIS) with 3D stack and in-pixel DTI.Y. Ji, J. Kim, J. Kim, M. Lee, J. Noh, T. Jeong, J. Shin, J. Kim, Y. Heo, U. Cho and 10 other author(s). IRPS, page 3. IEEE, (2018)Reliability of fine pitch COF: Influence of surface morphology and CuSn intermetallic compound formation.J. Park, M. Lee, K. Min, J. Choi, C. Joo, S. Park, H. Kang, and S. Pae. IRPS, page 4. IEEE, (2015)Effects of front-end-of line process variations and defects on retention failure of flash memory: Charge loss/gain mechanism.J. Park, M. Lee, H. Kang, W. Ko, E. Choi, J. Im, M. Lee, D. Chung, J. Park, S. Shin and 1 other author(s). IRPS, page 2. IEEE, (2015)Radiation-induced soft error rate analyses for 14 nm FinFET SRAM devices.S. Lee, I. Kim, S. Ha, C. sik Yu, J. Noh, S. Pae, and J. Park. IRPS, page 4. IEEE, (2015)SEIFF: Soft Error Immune Flip-Flop for Mitigating Single Event Upset and Single Event Transient in 10 nm FinFET.T. Uemura, S. Lee, D. Min, I. Moon, S. Lee, and S. Pae. IRPS, page 1-6. IEEE, (2019)Investigation of alpha-induced single event transient (SET) in 10 nm FinFET logic circuit.T. Uemura, S. Lee, D. Min, I. Moon, J. Lim, S. Lee, H. Sagong, and S. Pae. IRPS, page 1. IEEE, (2018)

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Reliability of 8Mbit Embedded-STT-MRAM in 28nm FDSOI Technology.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Reliability of 8Mbit Embedded-STT-MRAM in 28nm FDSOI Technology.

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Reliability of 8Mbit Embedded-STT-MRAM in 28nm FDSOI Technology.