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Disambiguation of "Cho, Kyoung-Rok"

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Backward Propagated Capacitance Model for Register Transfer Level Power Estimation.

, , and . VLSI Design, 2001 (2): 221-231 (2001)

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Hyeongrae Cho University of Stuttgart

Michel Choudalakis University of Stuttgart

Gretchen Chojnacki-Herbers University of Stuttgart

King Cho Wong University of Stuttgart

 

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Efficient co-simulation framework enhancing system-level power estimation for a platform-based SoC design., , , and . Microelectronics Journal, 42 (11): 1290-1298 (2011)Design of D-PHY chip for mobile display interface supporting MIPI standard., , and . Microelectronics Journal, 43 (12): 949-955 (2012)Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's., , and . IEICE Transactions, 91-C (1): 72-80 (2008)Priority-based dynamic bandwidth allocation in Ethernet Passive Optical Networks., , and . Photonic Network Communications, 15 (3): 203-212 (2008)Design of Asynchronous Embedded Processor with New Ternary Data Encoding Scheme., , and . SAMOS, volume 4017 of Lecture Notes in Computer Science, page 395-405. Springer, (2006)Memristor-based Synaptic Networks and Logical Operations Using In-Situ Computing, , , , , , and . CoRR, (2011)Formulation and Implementation of Nonlinear Integral Equations to Model Neural Dynamics Within the Vertebrate Retina., , , , , , , , and . Int. J. Neural Syst., 28 (7): 1850004:1-1850004:24 (2018)Optimum reserved resource allocation scheme for handoff in CDMA cellular system., , and . Journal of Systems Architecture, 46 (2): 131-144 (2000)High Fill Factor Low-Voltage CMOS Image Sensor Based on Time-to-Threshold PWM VLSI Architecture., , , and . IEEE Trans. VLSI Syst., 22 (7): 1548-1556 (2014)Design of a high performance self-timed ARM9 processor., and . IEICE Electronic Express, 5 (3): 87-93 (2008)