PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Farine, Pierre-André"

Author of the publication

copydeleteadd this publication to your clipboard
Performance Analysis of a Hybrid Incremental and Cyclic A/D Conversion Principle.

, , and . IEEE Trans. on Circuits and Systems, 56-I (7): 1383-1390 (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

André Jaquemod University of Stuttgart

Univ. -Prof. Dr. -Ing. André Zimmermann University of Stuttgart

75 Jahre Institut für Mikrointegration (IFM) Universität Stuttgart, and . Stuttgart, Universität Stuttgart, Institut für Mikrointegration, (2019)

Univ. -Prof. Dr. rer. nat. André Thess University of Stuttgart

Dr. -Ing. André Buchau University of Stuttgart

André Weiß University of Stuttgart

 

Other publications of authors with the same name

CPT Cesium-Cell Atomic Clock Operation With a 12-mW Frequency Synthesizer ASIC., , , , , , and . IEEE Trans. Instrumentation and Measurement, 64 (1): 263-270 (2015)Phase and frequency self-configurable efficient low voltage harvester for zero power wearable devices., , and . ESSCIRC, page 495-498. IEEE, (2016)Low-Power Manhattan Distance Calculation Circuit for Self-Organizing Neural Networks Implemented in the CMOS Technology., , , and . ESANN, (2012)Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 169-178. Springer, (2004)Performance comparison of UWB impulse-based multiple access schemes in indoor multipath channels., , , and . WPNC, page 89-94. IEEE, (2008)A 16-bit, 150-µW, 1-kS/s ADC with hybrid incremental and cyclic conversion scheme., , and . ICECS, page 751-754. IEEE, (2009)A novel 1V, 24µW, ΣΔ modulator using Amplifier & Comparator Based Switched Capacitor technique, with 10-kHz bandwidth and 64dB SNDR., , and . ICECS, page 1124-1127. IEEE, (2010)Implementation Issues of Kohonen Self-Organizing Map Realized on FPGA., , , , and . ESANN, (2012)A novel homomorphic processing of ultrasonic echoes for layer thickness measurement., , , and . IEEE Trans. Signal Processing, 40 (7): 1819-1825 (1992)Development of a versatile low-power 24 GHz phased array front-end in 90 nm CMOS technology., , , , , and . NEWCAS, page 465-468. IEEE, (2012)