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A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS.

D. Jeon, M. Seok, C. Chakrabarti, D. Blaauw, and D. Sylvester. J. Solid-State Circuits, 47 (1): 23-34 (2012)

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Moon Kwang Jeong University of Stuttgart

Moon Young Jeong University of Stuttgart

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A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS.D. Jeon, M. Seok, C. Chakrabarti, D. Blaauw, and D. Sylvester. J. Solid-State Circuits, 47 (1): 23-34 (2012)A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory.D. Jeon, Q. Dong, Y. Kim, X. Wang, S. Chen, H. Yu, D. Blaauw, and D. Sylvester. VLSIC, page 48-. IEEE, (2015)Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design.M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw, and D. Sylvester. DAC, page 990-995. ACM, (2011)Extending energy-saving voltage scaling in ultra low voltage integrated circuit designs.M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw, and D. Sylvester. ICICDT, page 1-4. IEEE, (2012)An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring.Y. Chen, D. Jeon, Y. Lee, Y. Kim, Z. Foo, I. Lee, N. Langhals, G. Kruger, H. Oral, O. Berenfeld and 3 other author(s). J. Solid-State Circuits, 50 (1): 375-390 (2015)A Multi-Channel Spike Sorting Processor With Accurate Clustering Algorithm Using Convolutional Autoencoder.C. Seong, W. Lee, and D. Jeon. IEEE Trans. Biomed. Circuits Syst., 15 (6): 1441-1453 (2021)Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS.S. Zeinolabedin, A. Do, D. Jeon, D. Sylvester, and T. Kim. APCCAS, page 734-735. IEEE, (2016)A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector.T. Jang, S. Jeong, D. Jeon, K. Choo, D. Sylvester, and D. Blaauw. J. Solid-State Circuits, 53 (1): 50-65 (2018)A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS.D. Jeon, Q. Dong, Y. Kim, X. Wang, S. Chen, H. Yu, D. Blaauw, and D. Sylvester. J. Solid-State Circuits, 52 (6): 1628-1642 (2017)A low-power VGA full-frame feature extraction processor.D. Jeon, Y. Kim, I. Lee, Z. Zhang, D. Blaauw, and D. Sylvester. ICASSP, page 2726-2730. IEEE, (2013)

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Disambiguation of "Jeon, Dongsuk"

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A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS.

Please choose a person to relate this publication to

Moon Kwang Jeong University of Stuttgart

Moon Young Jeong University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Jeon, Dongsuk"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS.

Please choose a person to relate this publication to

Moon Kwang Jeong University of Stuttgart

Moon Young Jeong University of Stuttgart

Other publications of authors with the same name

Disambiguation

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A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS.