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A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS.

H. Zhuo, Y. Li, W. Rhee, and Z. Wang. VLSI-DAT, page 1-4. IEEE, (2014)

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All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs.Y. Liu, W. Rhee, D. Friedman, and D. Ham. ISSCC, page 176-595. IEEE, (2007)A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL.X. Huang, K. Zeng, Y. Liu, W. Rhee, T. Kim, and Z. Wang. CICC, page 1-4. IEEE, (2019)A 9mW 6-9GHz 2.5Gb/s Proximity Transmitter with Combined OOK/BPSK Modulation for Low Power Mobile Connectivity.Y. Liu, H. Song, K. Zeng, W. Rhee, and Z. Wang. VLSI-DAT, page 1-4. IEEE, (2019)A Capacitor-Less Ripple-Less Hybrid LDO With Exponential Ratio Array and 4000x Load Current Range.Y. Zhang, H. Song, R. Zhou, W. Rhee, I. Shim, and Z. Wang. IEEE Trans. on Circuits and Systems, 66-II (1): 36-40 (2019)A Gated FM-UWB System With Data-Driven Front-End Power Control.B. Zhou, J. Qiao, R. He, J. Liu, W. Zhang, H. Lv, W. Rhee, Y. Li, and Z. Wang. IEEE Trans. on Circuits and Systems, 59-I (6): 1348-1358 (2012)A 2.5GHz ADPLL with PVT-insensitive ΔΣ dithered time-to-digital conversion by utilizing an ADDLL.Y. Li, N. Xu, W. Rhee, and Z. Wang. ISCAS, page 1440-1443. IEEE, (2014)A high efficiency robust IR-UWB receiver design for high data rate CM-range communications.D. Liu, S. Geng, W. Rhee, and Z. Wang. ISCAS, page 1901-1904. IEEE, (2014)Semidigital PLL Design for Low-Cost Low-Power Clock Generation.N. Xu, W. Rhee, and Z. Wang. J. Electrical and Computer Engineering, (2011)Experimental Analysis of Substrate Noise Effect on PLL Performance.W. Rhee, K. Jenkins, J. Liobe, and H. Ainspan. IEEE Trans. on Circuits and Systems, 55-II (7): 638-642 (2008)A ΔΣ-TDC-Based Beamforming Method for Vital Sign Detection Radar Systems.X. Chen, W. Zhang, W. Rhee, and Z. Wang. IEEE Trans. on Circuits and Systems, 61-II (12): 932-936 (2014)

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A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS.

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A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS.