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Machine Learning-Based Microarchitecture- Level Power Modeling of CPUs

, , , and . IEEE transactions on computers, 72 (4): 941-956 (2023)
DOI: 10.1109/TC.2022.3185572

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Dynamic power and performance back-annotation for fast and accurate functional hardware simulation., , and . DATE, page 1126-1131. ACM, (2015)Toward a fast stochastic simulation processor for biochemical reaction networks., and . ASAP, page 50-58. IEEE Computer Society, (2013)Introduction to hardware-dependent software design hardware-dependent software for multi- and many-core embedded systems., , and . ASP-DAC, page 290-292. IEEE, (2009)Optimizing GPGPU Kernel Summation for Performance and Energy Efficiency., , , , and . ICPP Workshops, page 123-132. IEEE Computer Society, (2016)Source-Level Performance, Energy, Reliability, Power and Thermal (PERPT) Simulation., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 36 (2): 299-312 (2017)RTOS scheduling in transaction level models., , and . CODES+ISSS, page 31-36. ACM, (2003)Automatic generation of transaction level models for rapid design space exploration., , , , and . CODES+ISSS, page 64-69. ACM, (2006)System-Level Abstraction Semantics., and . ISSS, page 231-236. ACM / IEEE Computer Society, (2002)The Formal Execution Semantics of SpecC., , and . ISSS, page 150-155. ACM / IEEE Computer Society, (2002)RTOS Modeling for System Level Design., , and . Embedded Software for SoC, Kluwer / Springer, (2003)