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Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.

A. Cassidy, R. Alvarez-Icaza, F. Akopyan, J. Sawada, J. Arthur, P. Merolla, P. Datta, M. Tallada, B. Taba, A. Andreopoulos, A. Amir, S. Esser, J. Kusnitz, R. Appuswamy, C. Haymes, B. Brezzo, R. Moussalli, R. Bellofatto, C. Baks, M. Mastro, K. Schleupen, C. Cox, K. Inoue, S. Millman, N. Imam, E. McQuinn, Y. Nakamura, I. Vo, C. Guok, D. Nguyen, S. Lekuch, S. Asaad, D. Friedman, B. Jackson, M. Flickner, W. Risk, R. Manohar, and D. Modha. SC, page 27-38. IEEE, (2014)

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Neural spiking dynamics in asynchronous digital circuits.N. Imam, K. Wecker, J. Tse, R. Karmazin, and R. Manohar. IJCNN, page 1-8. IEEE, (2013)A Digital Neurosynaptic Core Using Event-Driven QDI Circuits.N. Imam, F. Akopyan, J. Arthur, P. Merolla, R. Manohar, and D. Modha. ASYNC, page 25-32. IEEE Computer Society, (2012)Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.A. Cassidy, R. Alvarez-Icaza, F. Akopyan, J. Sawada, J. Arthur, P. Merolla, P. Datta, M. Tallada, B. Taba, A. Andreopoulos and 28 other author(s). SC, page 27-38. IEEE, (2014)Rapid online learning and robust recall in a neuromorphic olfactory circuit.N. Imam, and T. Cleland. CoRR, (2019)Building block of a programmable neuromorphic substrate: A digital neurosynaptic core.J. Arthur, P. Merolla, F. Akopyan, R. Alvarez-Icaza, A. Cassidy, S. Chandra, S. Esser, N. Imam, W. Risk, D. Rubin and 2 other author(s). IJCNN, page 1-8. IEEE, (2012)Address-Event Communication Using Token-Ring Mutual Exclusion.N. Imam, and R. Manohar. ASYNC, page 99-108. IEEE Computer Society, (2011)Loihi: A Neuromorphic Manycore Processor with On-Chip Learning.M. Davies, N. Srinivasa, T. Lin, G. Chinya, Y. Cao, S. Choday, G. Dimou, P. Joshi, N. Imam, S. Jain and 13 other author(s). IEEE Micro, 38 (1): 82-99 (2018)Design of a QDI asynchronous AER serializer/deserializer link in 180nm for event-based sensors for robotic applications.G. Rovere, C. Bartolozzi, N. Imam, and R. Manohar. ISCAS, page 2712-2715. IEEE, (2015)A memory-efficient routing method for large-scale spiking neural networks.S. Moradi, N. Imam, R. Manohar, and G. Indiveri. ECCTD, page 1-4. IEEE, (2013)A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm.P. Merolla, J. Arthur, F. Akopyan, N. Imam, R. Manohar, and D. Modha. CICC, page 1-4. IEEE, (2011)

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.

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