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Fault tolerant routing for hierarchically organized networks-on-chip

G. Schley, and M. Radetzki. 23rd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), page 379-386. Piscataway, NJ, IEEE, (2015)
DOI: 10.1109/PDP.2015.36

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Univ. -Prof. Dr. -Ing. Martin Radetzki University of Stuttgart

Martin Baumann

Martin Schwartz University of Stuttgart

Martin Alvarez University of Stuttgart

Univ. -Prof. Martin Ostermann University of Stuttgart

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Optimal placement of vertical connections in 3D Network-on-Chip.T. Xu, G. Schley, P. Liljeberg, M. Radetzki, J. Plosila, and H. Tenhunen. Journal of Systems Architecture - Embedded Systems Design, 59 (7): 441-454 (2013)Intelligent IP retrieval driven by application requirements.M. Schaaf, A. Freßmann, R. Maximini, R. Bergmann, A. Tartakovski, and M. Radetzki. Integration, 37 (4): 253-287 (2004)A case study on message-based discrete event simulation for Transaction Level Modeling.B. Haetzer, and M. Radetzki. FDL, page 1-8. IEEE, (2011)A Latency, Preemption and Data Transfer Accurate Adaptive Transaction Level Model for Efficient Simulation of Pipelined Buses.R. Khaligh, and M. Radetzki. FDL, page 37-42. IEEE, (2008)Power Management for High-Performance Applications on Network-on-Chip-Based Multiprocessors.A. Kohler, and M. Radetzki. GreenCom/iThings/CPScom, page 77-85. IEEE, (2013)Efficient Fault Simulation of SystemC Designs.W. Lu, and M. Radetzki. DSD, page 487-494. IEEE Computer Society, (2011)A methodology to compute long-term fault resilience of NoCs under fault-tolerant routing algorithmsJ. Hou, and M. Radetzki. 2019 Forum for Specification and Design Languages (FDL), Piscataway, IEEE, (2019)A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCsJ. Hou, Q. Han, and M. Radetzki. 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)), page 164-171. Piscataway, IEEE, (2019)Qualität und Qualitätssicherung wiederverwendbarer Schaltungsbeschreibungen (Quality and Quality Assurance of Reusable Circuit Descriptions).M. Radetzki. it+ti - Informationstechnik und Technische Informatik, 44 (2): 99-102 (2002)Modelling Alternatives for Cycle Approximate Bus TLMs.M. Radetzki, and R. Khaligh. FDL, page 74-79. ECSI, (2007)