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Efficient RT-Level Fault Diagnosis., and . J. Comput. Sci. Technol., 20 (2): 166-174 (2005)Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (2): 298-302 (2009)Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (5): 822-834 (2015)Construction of an adaptive scan network for test time and data volume reduction.. IET Computers & Digital Techniques, 2 (1): 12-22 (2008)Multi-modal response compaction adaptive to x-density variation., and . IET Computers & Digital Techniques, 6 (2): 69-77 (2012)Novel hazard-free majority voter for n-modular redundancy-based fault tolerance in asynchronous circuits., and . IET Computers & Digital Techniques, 5 (4): 306-315 (2011)Testing Chips With Spare Identical Cores., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (7): 1124-1135 (2013)Isolation Techniques for Soft Cores., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (8): 1453-1466 (2008)Sneak-path Testing of Memristor-based Memories., , , and . VLSI Design, page 386-391. IEEE Computer Society, (2013)Revival of partial scan: Test cube analysis driven conversion of flip-flops., and . VTS, page 260-265. IEEE Computer Society, (2011)