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Representative Multiprogram Workloads for Multithreaded Processor Simulation., , and . IISWC, page 193-203. IEEE Computer Society, (2007)A Counter Architecture for Online DVFS Profitability Estimation., and . IEEE Trans. Computers, 59 (11): 1576-1583 (2010)Chip Multiprocessor Design Space Exploration through Statistical Simulation., and . IEEE Trans. Computers, 58 (12): 1668-1681 (2009)Memory Data Flow Modeling in Statistical Simulation for the Efficient Exploration of Microprocessor Design Spaces., and . IEEE Trans. Computers, 57 (1): 41-54 (2008)Using cycle stacks to understand scaling bottlenecks in multi-threaded workloads., , , , and . IISWC, page 38-49. IEEE Computer Society, (2011)Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces., and . IEEE PACT, page 25-34. IEEE Computer Society, (2001)Workload Design: Selecting Representative Program-Input Pairs., , and . IEEE PACT, page 83-94. IEEE Computer Society, (2002)Adaptive Prefetching for Multimedia Applications in Embedded Systems., , and . DATE, page 1350-1351. IEEE Computer Society, (2004)Improved composite confidence mechanisms for a perceptron branch predictor., , and . Journal of Systems Architecture, 52 (3): 143-151 (2006)Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox., , , and . IEEE Micro, 23 (5): 26-38 (2003)