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Analysis of Logic Circuits with Faults Using Input Signal Probabilities., and . IEEE Trans. Computers, 24 (5): 573-578 (1975)Logic Design of Multivalued I2L Logic Circuits.. IEEE Trans. Computers, 28 (8): 546-559 (1979)Pseudorandom Testing., , and . IEEE Trans. Computers, 36 (3): 332-343 (1987)Procedure Call Duplication: Minimization of Energy Consumption with Constrained Error Detection Latency., and . DFT, page 182-. IEEE Computer Society, (2001)Test and Diagnosis Procedure for Digital Networks.. IEEE Computer, 4 (1): 17-20 (1971)Summary of Structural integrity Checking., , and . RTSS, page 107-109. IEEE Computer Society, (1980)Experimental Results for IDDQ and VLV Testing., , , , , and . VTS, page 118-125. IEEE Computer Society, (1998)Error Sequence Analysis., , and . VTS, page 255-260. IEEE Computer Society, (2008)High-Level Synthesis for Orthogonal Sca., and . VTS, page 370-375. IEEE Computer Society, (1997)A simple technique for locating gate-level faults in combinational circuits., , and . Asian Test Symposium, page 65-70. IEEE Computer Society, (1995)