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A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation., , , , and . IEEE Trans. on Circuits and Systems, 63-I (2): 181-190 (2016)Quick detection of difficult bugs for effective post-silicon validation., , , , and . DAC, page 561-566. ACM, (2012)Post-silicon validation challenges: how EDA and academia can help., , and . DAC, page 3-7. ACM, (2010)Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage., , , , , , , , , and 2 other author(s). ISLPED, page 26-29. ACM, (2005)Innovative practices session 1C: Post-silicon validation., and . VTS, page 1-2. IEEE Computer Society, (2013)Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (4): 733-740 (2019)Coping with Uncertainty.. ISQED, page 9. IEEE Computer Society, (2004)Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation., , and . ITC, page 1-10. IEEE, (2018)The care and feeding of your statistical static timer., , and . ICCAD, page 138-139. IEEE Computer Society / ACM, (2004)A hybrid electrical-behavioral modeling approach for pre- and post-silicon electrical validation., , , and . CICC, page 1-5. IEEE, (2012)