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Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware.

, , , , , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 264-274. Springer, (2001)

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The Formal Semantics Definition of a Multi-Rate DSP Specification Language in HOL., , and . TPHOLs, volume A-20 of IFIP Transactions, page 375-394. North-Holland/Elsevier, (1992)Flexible hardware acceleration for multimedia oriented microprocessors., , , , and . MICRO, page 171-177. ACM/IEEE Computer Society, (2000)Platform Independent Data Transfer and Storage Exploration Illustrated on Parallel Cavity Detection Algorithm., , and . PDPTA, page 1669-1675. CSREA Press, (1999)Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling., , , , and . DATE, page 10296-10301. IEEE Computer Society, (2003)Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver., , , , , and . DATE, page 10642-10649. IEEE Computer Society, (2003)Design Technology Research and Education for Deep-Submicron Systems of the Next Century.. VTS, page 8-15. IEEE Computer Society, (1999)Multi-thread graph: a system model for real-time embedded software synthesis., , , , and . ED&TC, page 476-481. IEEE Computer Society, (1997)On Nanoscale Integration and Gigascale Complexity in the Post.Com World.. DATE, page 12. IEEE Computer Society, (2002)Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment., , , , and . EURO-DAC, page 208-213. EEE Computer Society, (1991)Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment., , and . EURO-DAC, page 62-66. IEEE Computer Society, (1990)