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Testing of Low-cost Digital Microfluidic Biochips with Non-Regular Array Layouts., , and . J. Electronic Testing, 28 (2): 243-255 (2012)Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (2): 352-365 (2008)Detection, Diagnosis, and Recovery From Clock-Domain Crossing Failures in Multiclock SoCs., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (9): 1395-1408 (2013)Board-Level Functional Fault Diagnosis Using Multikernel Support Vector Machines and Incremental Learning., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (2): 279-290 (2014)Robust Optimization of Test-Access Architectures Under Realistic Scenarios., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (11): 1873-1884 (2015)Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (1): 111-120 (2009)Reproduction and Detection of Board-Level Functional Failure., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (4): 630-643 (2012)Board-Level Functional Fault Diagnosis Using Artificial Neural Networks, Support-Vector Machines, and Weighted-Majority Voting., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (5): 723-736 (2013)Guest Editorial.. J. Electronic Testing, 18 (4-5): 363 (2002)Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults., , , , , and . J. Electronic Testing, 29 (1): 35-48 (2013)