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Architecture-driven voltage scaling for high-throughput turbo-decoders., , and . J. Embedded Computing, 1 (3): 391-402 (2005)A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding., and . SiPS, page 142-147. IEEE, (2006)Evaluation of algorithm optimizations for low-power Turbo-Decoder implementations., , , and . ICASSP, page 3101-3104. IEEE, (2002)Row-Merged Polar Codes: Analysis, Design and Decoder Implementation, , , , , , and . (2023)A Scalable System Architecture for High-Throughput Turbo-Decoders., , , , and . VLSI Signal Processing, 39 (1-2): 63-77 (2005)A Reconfigurable Outer Modem Platform for Future Communications Systems., , and . Dynamically Reconfigurable Architectures, volume 06141 of Dagstuhl Seminar Proceedings, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, (2006)Application-specific reconfigurable processors., , , , , , , and . FPL, page 350. IEEE, (2008)A multi-standard channel-decoder for base-station applications., , and . SBCCI, page 192-197. ACM, (2004)A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment., and . IEEE Trans. VLSI Syst., 16 (10): 1309-1320 (2008)FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems., , , and . Dynamically Reconfigurable Systems, Springer, (2010)