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Statistical Clock Skew Analysis Considering Intra-Die Process Variations.

, , and . ICCAD, page 914-921. IEEE Computer Society / ACM, (2003)

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Statistical clock skew analysis considering intradie-process variations., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (8): 1231-1242 (2004)Statistical timing analysis using bounds and selective enumeration., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 22 (9): 1243-1260 (2003)Computation and Refinement of Statistical Bounds on Circuit Delay., , , and . DAC, page 348-353. ACM, (2003)Circuit optimization using statistical static timing analysis., , , and . DAC, page 321-324. ACM, (2005)Statistical Timing Based Optimization using Gate Sizing., , and . DATE, page 400-405. IEEE Computer Society, (2005)Statistical delay computation considering spatial correlations., , , , , , and . ASP-DAC, page 271-276. ACM, (2003)Statistical Timing Based Optimization using Gate Sizing, , and . CoRR, (2007)Statistical gate delay model considering multiple input switching., , and . DAC, page 658-663. ACM, (2004)Statistical Timing Analysis Using Bounds., , , and . DATE, page 10062-10067. IEEE Computer Society, (2003)Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations., , and . ICCAD, page 900-907. IEEE Computer Society / ACM, (2003)