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A DRAM Centric NoC Architecture and Topology Design Approach.

, , , and . ISVLSI, page 54-59. IEEE Computer Society, (2011)

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3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks., , , and . 3D Integration for NoC-based SoC Architectures, Springer, (2011)SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (12): 1987-2000 (2010)3.5-D integration: A case study., , , , and . ISCAS, page 2087-2090. IEEE, (2013)A DRAM Centric NoC Architecture and Topology Design Approach., , , and . ISVLSI, page 54-59. IEEE Computer Society, (2011)A floorplan-aware interactive tool flow for NoC design and synthesis., , , , , and . SoCC, page 379-382. IEEE, (2009)A distributed interleaving scheme for efficient access to WideIO DRAM memory., , and . CODES+ISSS, page 103-112. ACM, (2012)NoC topology synthesis for supporting shutdown of voltage islands in SoCs., , , and . DAC, page 822-825. ACM, (2009)Design and Analysis of NoCs for Low-Power 2D and 3D SoCs., , , and . Low Power Networks-on-Chip, Springer, (2011)Synthesis of networks on chips for 3D systems on chips., , , and . ASP-DAC, page 242-247. IEEE, (2009)Networks on Chips: from research to products., , , , , and . DAC, page 300-305. ACM, (2010)