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Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.

, , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (5): 896-906 (2007)

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Facilitating Rapid First Silicon Debug., , and . ITC, page 628-637. IEEE Computer Society, (2002)What we know after twelve years developing and deploying test data analytics solutions., , and . ITC, page 1-8. IEEE, (2016)The roles of controllability and observability in design for test., , , and . VTS, page 211-216. IEEE Computer Society, (1992)Test Generation and Design for Test for a Large Multiprocessing DSP., , , and . ITC, page 149-156. IEEE Computer Society, (1995)Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling., , , , , and . ITC, page 1-10. IEEE Computer Society, (2014)CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology., , , and . DAC, page 597-600. (1988)Modeling Test Escape Rate as a Function of Multiple Coverages., , and . ITC, page 1-9. IEEE Computer Society, (2008)An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing., , , , and . VTS, page 459. IEEE Computer Society, (1997)Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (5): 896-906 (2007)Fast functional evaluation of candidate OBDD variable orderings., , , and . EURO-DAC, page 4-10. EEE Computer Society, (1991)