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Prediction Based DRAM Row-Buffer Management in the Many-Core Era., , , and . PACT, page 183-184. IEEE Computer Society, (2011)Handling the problems and opportunities posed by multiple on-chip memory controllers., , , , and . PACT, page 319-330. ACM, (2010)Beyond block I/O: Rethinking traditional storage primitives., , , , and . HPCA, page 301-311. IEEE Computer Society, (2011)Selective GPU caches to eliminate CPU-GPU HW cache coherence., , , , , and . HPCA, page 494-506. IEEE Computer Society, (2016)Hardware prediction of OS run-length for fine-grained resource customization., , , and . ISPASS, page 111-112. IEEE Computer Society, (2010)Micro-pages: increasing DRAM efficiency with locality-aware data placement., , , , , and . ASPLOS, page 219-230. ACM, (2010)Beyond the socket: NUMA-aware GPUs., , , , , , , and . MICRO, page 123-135. ACM, (2017)Scaling the Power Wall: A Path to Exascale., , , , , , , , , and 2 other author(s). SC, page 830-841. IEEE, (2014)SWEL: hardware cache coherence protocols to map shared data onto shared caches., , , and . PACT, page 465-476. ACM, (2010)Understanding the Future of Energy Efficiency in Multi-Module GPUs., , , and . HPCA, page 519-532. IEEE, (2019)