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Beyond the socket: NUMA-aware GPUs.

U. Milic, O. Villa, E. Bolotin, A. Arunkumar, E. Ebrahimi, A. Jaleel, A. Ramírez, and D. Nellans. MICRO, page 123-135. ACM, (2017)

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Understanding the Memory Behavior of Emerging Multi-core Workloads.J. Lin, Y. Chen, W. Li, A. Jaleel, and Z. Tang. ISPDC, page 153-160. IEEE Computer Society, (2009)Fairness-aware scheduling on single-ISA heterogeneous multi-cores.K. Craeynest, S. Akram, W. Heirman, A. Jaleel, and L. Eeckhout. PACT, page 177-187. IEEE Computer Society, (2013)In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs).A. Jaleel, and B. Jacob. IEEE Trans. Computers, 55 (5): 559-574 (2006)LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches.H. Cheng, J. Zhao, J. Sampson, M. Irwin, A. Jaleel, Y. Lu, and Y. Xie. ISCA, page 103-114. IEEE Computer Society, (2016)CANDY: Enabling coherent DRAM caches for multi-node systems.C. Chou, A. Jaleel, and M. Qureshi. MICRO, page 1-13. IEEE Computer Society, (2016)HAPPY: Hybrid Address-based Page Policy in DRAMs.M. Ghasempour, A. Jaleel, J. Garside, and M. Luján. CoRR, (2015)Adaptive memory-side last-level GPU caching.X. Zhao, A. Adileh, Z. Yu, Z. Wang, A. Jaleel, and L. Eeckhout. ISCA, page 411-423. ACM, (2019)Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers.S. Pugsley, Z. Chishti, C. Wilkerson, P. fei Chuang, R. Scott, A. Jaleel, S. Lu, K. Chow, and R. Balasubramonian. HPCA, page 626-637. IEEE Computer Society, (2014)High performance cache replacement using re-reference interval prediction (RRIP).A. Jaleel, K. Theobald, S. Jr., and J. Emer. ISCA, page 60-71. ACM, (2010)CMPSched$im: Evaluating OS/CMP interaction on shared cache management.J. Moses, K. Aisopos, A. Jaleel, R. Iyer, R. Illikkal, D. Newell, and S. Makineni. ISPASS, page 113-122. IEEE Computer Society, (2009)

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Beyond the socket: NUMA-aware GPUs.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Beyond the socket: NUMA-aware GPUs.

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Beyond the socket: NUMA-aware GPUs.