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Parasitic Extraction for Silicon MOSFETs

, , , , and . International IEEE MTT/AP Workshop on MMIC Design, Packaging, and System Applications, page 23--24. Freiburg, Germany, Fraunhofer Inst. for Applied Solid State Physics, (1998)

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0.5V CMOS logic delivering 200 million 8*8 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technology., , , and . ISLPED, page 103-105. ACM, (1998)Parasitic Extraction for Silicon MOSFETs, , , , and . International IEEE MTT/AP Workshop on MMIC Design, Packaging, and System Applications, page 23--24. Freiburg, Germany, Fraunhofer Inst. for Applied Solid State Physics, (1998)Experimental Results of a Comparative Study with Passive Structures using a Standard 0.8 µm CMOS Process, , , and . International IEEE MTT/AP Workshop on MMIC Design, Packaging, and System Applications, page 52--55. Freiburg, Germany, Fraunhofer Inst. for Applied Solid State Physics, (1998)