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Analysis and optimization of NBTI induced clock skew in gated clock trees., , , and . DATE, page 296-299. IEEE, (2009)Performance analysis of 3-D monolithic integrated circuits., , , , , and . 3DIC, page 1-4. IEEE, (2010)Implementation of a thermal management unit for canceling temperature-dependent clock skew variations., , , , , , and . Integration, 41 (1): 2-8 (2008)Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective., , , , , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 214-224. Springer, (2006)Controlling NBTI degradation during static burn-in testing., and . ASP-DAC, page 597-602. IEEE, (2011)Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs., , , , , and . IEEE Trans. on Circuits and Systems, 57-I (10): 2741-2752 (2010)An integrated nonlinear placement framework with congestion and porosity aware buffer planning., , and . DAC, page 702-707. ACM, (2008)Thermal resilient bounded-skew clock tree optimization methodology., , , , , and . DATE, page 832-837. European Design and Automation Association, Leuven, Belgium, (2006)Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits., , , , , , and . ISCAS, IEEE, (2006)Low-Voltage, Double-Edge-Triggered Flip Flop., and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 11-20. Springer, (2003)