PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Duraisami, Karthik"

Author of the publication

copydeleteadd this publication to your clipboard
Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.

, , , , , and . IEEE Trans. on Circuits and Systems, 57-I (10): 2741-2752 (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Karthik Pandaram University of Stuttgart

 

Other publications of authors with the same name

Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers., , , , , , , and . IEEE Trans. VLSI Syst., 16 (6): 639-649 (2008)Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs., , , , , and . IEEE Trans. on Circuits and Systems, 57-I (10): 2741-2752 (2010)Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew., , , , , and . ISCAS, page 1061-1064. IEEE, (2007)Implementation of a thermal management unit for canceling temperature-dependent clock skew variations., , , , , , and . Integration, 41 (1): 2-8 (2008)Using soft-edge flip-flops to compensate NBTI-induced delay degradation., , and . ACM Great Lakes Symposium on VLSI, page 169-172. ACM, (2009)Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective., , , , , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 214-224. Springer, (2006)Thermal resilient bounded-skew clock tree optimization methodology., , , , , and . DATE, page 832-837. European Design and Automation Association, Leuven, Belgium, (2006)Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits., , , , , , and . ISCAS, IEEE, (2006)Thermal-Aware Design Techniques for Nanometer CMOS Circuits., , , , , , , and . J. Low Power Electronics, 4 (3): 374-384 (2008)Energy efficiency bounds of pulse-encoded buses., , and . ACM Great Lakes Symposium on VLSI, page 183-188. ACM, (2008)