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A novel low-power physical design methodology for MTCMOS.

X. Zhao, Y. Cai, Q. Zhou, and X. Hong. ISCAS, IEEE, (2006)

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Other publications of authors with the same name

Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain.Y. Cai, J. Shi, Z. Luo, and X. Hong. J. Comput. Sci. Technol., 20 (2): 224-230 (2005)Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths.Z. Qi, Y. Cai, and Q. Zhou. J. Comput. Sci. Technol., 30 (3): 614-628 (2015)Priority-Based Routing Resource Assignment Considering Crosstalk.Y. Cai, B. Liu, Y. Xiong, Q. Zhou, and X. Hong. J. Comput. Sci. Technol., 21 (6): 913-921 (2006)Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.W. Shen, Y. Cai, X. Hong, and J. Hu. ISVLSI, page 383-388. IEEE Computer Society, (2007)A thermal-driven force-directed floorplanning algorithm for 3D ICs.Y. Huang, Q. Zhou, Y. Cai, and H. Yan. CAD/Graphics, page 497-502. IEEE, (2009)Bridging the Gap between Global Routing and Detailed Routing: A Practical Congestion Model.Z. Qi, Y. Cai, and Q. Zhou. CAD/Graphics, page 74-80. IEEE, (2013)A novel fine-grain track routing approach for routability and crosstalk optimization.Z. Qi, Q. Zhou, Y. Jia, Y. Cai, Z. Li, and H. Yao. ISQED, page 621-626. IEEE, (2011)Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan.X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C. Cheng, and J. Gu. ICCAD, page 8-12. IEEE Computer Society, (2000)SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography.Z. Chen, H. Yao, and Y. Cai. ISQED, page 566-571. IEEE, (2013)DFM-aware Routing for Yield Enhancement.X. Hong, Y. Cai, H. Yao, and D. Li. APCCAS, page 1091-1094. IEEE, (2006)

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A novel low-power physical design methodology for MTCMOS.

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Disambiguation of "Cai, Yici"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A novel low-power physical design methodology for MTCMOS.

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A novel low-power physical design methodology for MTCMOS.