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A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications.

, , , , and . IPDPS Workshops, page 265-270. IEEE Computer Society, (2016)

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Improving reconfiguration speed for dynamic circuit specialization using placement constraints., , , and . ReConFig, page 1-6. IEEE, (2014)Performance Evaluation of Dynamic Circuit Specialization on Xilinx FPGAs., , , and . FPGAworld, page 1:1-1:6. ACM, (2014)SICTA: A superimposed in-circuit fault tolerant architecture for SRAM-based FPGAs., , and . IOLTS, page 5-8. IEEE, (2017)A 16-Bit Reconfigurable Encryption Processor for p-Cipher., , , , , and . IPDPS Workshops, page 162-171. IEEE Computer Society, (2016)MiCAP: a custom reconfiguration controller for dynamic circuit specialization., , and . ReConFig, page 1-6. IEEE, (2015)HyperLogLog Sketch Acceleration on FPGA., , , , , and . FPL, page 47-56. IEEE, (2020)A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications., , , , and . IPDPS Workshops, page 265-270. IEEE Computer Society, (2016)Response to "Comment on 'Short-Term Arterial Travel Time Prediction for Advanced Traveler Information Systems' by Wei-Hua Lin, Amit Kulkarni, and Pitu Mirchandani"., , and . J. Intellig. Transport. Systems, 10 (1): 45-47 (2006)EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures., , , , , , , , , and 9 other author(s). ReCoSoC, page 1-7. IEEE, (2016)Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications., , , , and . CoRR, (2017)