Author of the publication

Testing Memories for Single-Cell Pattern-Sensitive Faults.

. IEEE Trans. Computers, 29 (3): 249-254 (1980)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Scalar-Vector Memory Interference in Vector Computers., and . ICPP (1), page 180-187. CRC Press, (1991)Architecture of a Hypercube Supercomputer., , and . ICPP, page 653-660. IEEE Computer Society Press, (1986)Testing Memories for Single-Cell Pattern-Sensitive Faults.. IEEE Trans. Computers, 29 (3): 249-254 (1980)Test Point Placement to Simplify Fault Detection., and . IEEE Trans. Computers, 23 (7): 727-735 (1974)Some Practical Issues in the Design of Fault-Tolerant Multiprocessors., and . IEEE Trans. Computers, 41 (5): 588-598 (1992)Detection of Pattern-Sensitive Faults in Random-Access Memories.. IEEE Trans. Computers, 24 (2): 150-157 (1975)A Fault-Tolerant Communication Scheme for Hypercube Computers., and . IEEE Trans. Computers, 41 (10): 1242-1256 (1992)A 3.6mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOS., , and . CICC, page 361-364. IEEE, (2005)An Analysis Framework for Transient-Error Tolerance., , and . VTS, page 249-255. IEEE Computer Society, (2007)The input pattern fault model and its application., and . ED&TC, page 628. IEEE Computer Society, (1997)