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Reduction methods for adapting optical network on chip topologies to 3D architectures.

S. Beux, I. O'Connor, G. Nicolescu, G. Bois, and P. Paulin. Microprocessors and Microsystems - Embedded Hardware Design, 37 (1): 87-98 (2013)

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SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS.J. Chevalier, M. Rondonneau, O. Benny, G. Bois, E. Aboulhamid, and F. Boyer. FDL, page 704-716. ECSI, (2003)An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept.K. Hadjiat, F. St-Pierre, G. Bois, Y. Savaria, M. Langevin, and P. Paulin. ICECS, page 995-998. IEEE, (2007)Communication Structure Refinement using Temporal Constraints Analysis.A. Tsikhanovich, E. Aboulhamid, and G. Bois. ICECS, page 1284-1287. IEEE, (2007)Combining mapping and partitioning exploration for NoC-based embedded systems.S. Beux, G. Bois, G. Nicolescu, Y. Bouchebaba, M. Langevin, and P. Paulin. Journal of Systems Architecture - Embedded Systems Design, 56 (7): 223-232 (2010)Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor.N. Beucher, N. Bélanger, Y. Savaria, and G. Bois. SiPS, page 130-135. IEEE, (2006)Design of Clock Distribution Networks in Presence of Process Variations.M. Nekili, Y. Savaria, and G. Bois. Great Lakes Symposium on VLSI, page 95-102. IEEE Computer Society, (1998)A novel low-overhead flexible instrumentation framework for virtual platforms.T. Carmel-Veilleux, J. Boland, and G. Bois. International Symposium on Rapid System Prototyping, page 92-98. IEEE, (2011)A Reprogrammable SoC Design for a Real-Time Control Application.J. Thibeault, M. Hubin, F. Deslauriers, P. Samson, and G. Bois. MSE, page 73-74. IEEE Computer Society, (2005)Development of a high performance TSPC library for implementation of large digital building blocks.B. Chapelain, A. Mechain, Y. Savaria, and G. Bois. ISCAS (1), page 443-446. IEEE, (1999)High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse.N. Beucher, N. Bélanger, Y. Savaria, and G. Bois. Signal Processing Systems, 56 (2-3): 155-165 (2009)

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Reduction methods for adapting optical network on chip topologies to 3D architectures.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Reduction methods for adapting optical network on chip topologies to 3D architectures.

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Reduction methods for adapting optical network on chip topologies to 3D architectures.